The present invention relates to a circuit for generating a clock signal from a composite received signal including both digital information and a timing component such as a frame synchronizing sequence. More particularly, the invention relates to such a clock generating circuit in which the locking state of a phase-locked loop used in the generation of the clock signal is detected and corrected as needed.
A so-called "eight-to-fourteen" modulation system, hereinafter referred to simply as an EFM system, has been employed in the transmission of digital data at high data rates. The digital data may be modulated according to the well-known PCM (Pulse Code Modulation) technique, and the modulation system may be applied to either data recorded on a recording medium such as a video disc or data transmitted over a communication link. In the demodulation of such signals, it has been customary to employ a phase-locked loop circuit to recover the clock signal from the composite information and timing signal in order to obtain a stable clock signal for use in clocking the recovered digital data. Such circuits suffer a significant drawback in that it sometimes occurs that the phase-locked loop circuit will lock onto other than the timing component in the composite received signal. In such a case, it is impossible to properly process the received digital data for lack of a clocking signal which has the proper frequency relationship to the digital data and which has pulses in the desired phase relationship thereto. Thus, in order to detect the fact that the phase-locked loop circuit has locked onto an incorrect component in the received signal, it is necessary to discriminate a properly locked state from a mislocked state.
With reference now to the block diagram of FIG. 1, a conventional phase-locked loop clock generating circuit which is capable of making the desired discrimination between locking states is shown. The received composite signal is applied to the input of an edge detector 1. The edge detector 1 generates a pulse for both rising and falling edges of the received composite signal. The output of the edge detector is fed to inputs of phase comparators 2 and 3. The composite signal in this case may be a signal read from a video disc which contains digital information representing both video and audio information and a frame synchronizing sequence. As per the usual construction, the phase-locked loop circuit 6 includes a phase comparator 2, loop filter 4 and voltage-controlled oscillator 5. The output of the edge detector 1 is compared with the output of the voltage controlled oscillator 5 by the phase comparator 2. The result of this comparison, a signal representing the difference in frequency and phase between the two signals, is applied through the loop filter 4 to the input of the voltage-controlled oscillator 5. The output of the voltage-controlled oscillator is applied to a decoding circuit (not shown) as the recovered clock signal, and also to the second input of the phase comparator 2 and to the input of a phase shifter 7. The phase shifted signal produced by the phase shifter 7 is compared with the output of the edge detector 1 by the phase comparator 3. The output signal from the phase comparator 3, representing the difference in phase between the output of the edge detector 1 and the output of the phase shifter 7, is applied to the input of a low-pass filter 8, and thence to a level comparator 9. The level comparator 9 compares the output of the low-pass filter 8 with a predetermined reference level and thereby produces a binary signal which indicates whether the output from the low-pass filter 8 is greater than or less than the reference level.
When the phase-locked loop circuit 6 has locked onto a signal, the phase difference seen by the phase comparator 2 is approximately zero. However, the phase difference seen by the phase comparator 3 is nonzero due to the phase difference imparted by the phase shifter 7. If the phase shift of the phase shifter is properly chosen, the output of the phase comparator 3 will be a maximum when the phase-locked loop is in its locked state. The output from the low-pass filter 8 will then exceed the predetermined reference level, and the output of the level comparator 9 will be in a state indicative of the locked state of the phase-locked loop circuit 6. In the described circuit, the phase shift imparted by the phase shifter 7 should be 90.degree. in the case that the phase comparators 2 and 3 are constructed so that maximum outputs therefrom are obtained when the input signals thereto differ in phase from one another by 90.degree..
Although the conventional system described above was in fact capable of making a discrimination between the locked and unlocked states of the phase-locked loop, nevertheless, it was not fully acceptable for many applications because, if the received signal contained a high frequency component in the same frequency range as the timing signal, the phase-locked loop could erroneously lock onto the wrong signal component and hence generate an erroneous clock signal.
This effect will now be explained in more detail with reference to the timing diagram of FIG. 2 which shows the waveform of a reproduced signal obtained from an optically recorded audio disc on which the audio information has been recorded using both PCM and EFM. As indicated in FIG. 2, one frame is composed of a predetermined number of bits, here assumed to be 588 bits. The 588-bit frame is converted into a format of eight bytes, each composed of 14 bits. Three parity bits are added to each 14-bit byte to make a total of 17 bits. The resulting signal is recorded according to the NRZI system whereby a change from a high logic level to low logic level is indicative of an information bit in the "1" state and a change from a low logic level to a high logic level corresponds to an information bit in the "0" state.
A frame synchronizing sequence is recorded by recording bits in particular locations in predetermined states. For the example presently under discussion, the first bit of each frame is a 1, the second to the eleventh bits are 0, the twelfth bit is 1, the thirteenth to the twenty-second bits are 0, and the twenty-third bit is 1. A control signal is disposed at a predetermined position relative to the frame synchronizing sequence. Signal processing is carried out such that not less than two or more than ten 0s are located between 1s. That is, the minimum bit reversal time is set to be 3T, where T is the period of a single bit of the 588-bit frame. As further indicated in FIG. 2, the maximum reversal interval is set to be 11T. The signal processing technique employed further assumes that no two maximum reversal intervals occur sequentially except for in the frame synchronizing sequence. Also, the states of the bits of the frame synchronizing sequence can be made to reverse for every other frame synchronizing sequence.
In "silent" portions of the disc, such as in the lead-in and lead-out grooves and during intersong intervals, the recorded signal will have a fixed pattern, having a sequence such as 7T, 3T, 7T . . . , repeating each 17 bits. When the corresponding recovered composite signal is demodulated, it will thus include a high frequency component which can be mistaken for the frame synchronizing sequence. More particularly, in a case where the frame bit rate is 4.3218 MHz, spurious signal components will be generated at frequencies of 4.3218.+-.n.times.254 KHz, where 254 KHz=4.3218 MHz.div.17, and n is an integer. If one of these components near in frequency to the frame synchronizing sequence has sufficient energy, the phase-locked loop circuit may lock onto the spurious component, causing the output from the level comparator 9 to be set in the state indicative of actual lock. This is, of course, an erroneous indication. Because in this system the clock signal is used to control the rotation speed of the disc, the speed of the disc may become erroneous, thus making it very difficult to ever properly recover the true clock signal. The conventional arrangement is thus disadvantageous in this respect. Also, it may noted that the prior art arrangement requires a rather cumbersome and complex circuit arrangement due to the necessity for providing the phase comparator 3, the phase shifter 7, the low-pass filter 8 and the level comparator 9.
It is thus an object of the invention to provide a clock generating circuit for use in recovering a clock signal using a phase-locked loop in which spurious lock of the phase-locked loop circuit is avoided.
It is a further object of the invention to provide such a clock generating circuit in which few components in addition to those necessary for the phase-locked loop circuit itself are required.